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    • 专利摘要:
    A device (60) for integrating an electric current during a period Tint comprises an operational amplifier (62), and a capacitor (64) connected between a first input and an output of the amplifier (62), a second the input of the amplifier (62) being brought to a voltage VBUS, the output voltage Vout of the amplifier (62) being saturated at a high voltage VsatH and a low voltage VsatH depending on the amount of charge in the capacitor ( 64). The device (60) also comprises: a circuit (72) for switching the terminals of the capacitor (64); and a circuit (74) for tripping the circuit (72) at least once during the duration Tint when the voltage Vout both increases and is substantially equal to a reference voltage VREF, said voltage VREF being less than or equal to the voltage VsatH, and the reference voltage VREF and the voltage VBUS (62) being chosen so as to satisfy the relation 2. VBUS - VREF ≥ VsatL; and a circuit (76) for storing the number of trips occurring between the initial instant and the final instant of the integration period.
    公开号:FR3020906A1
    申请号:FR1454119
    申请日:2014-05-07
    公开日:2015-11-13
    发明作者:Patrick Robert
    申请人:Ulis SAS；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The invention relates to the field of electrical current integration, in particular that of integrators comprising a capacitor connected in feedback on an operational amplifier and delivering a voltage that is a function of the charges received and stored in the capacitor.
    [0002] The invention applies in particular, but not exclusively, to the field of the detection of electromagnetic radiation, and particularly that of the infrared. It applies more specifically to the field of thermal imaging using matrix detectors consisting of a matrix of micro-bolometers, whether it is the conventional imaging intended to form thermal images, or of thermographic imaging to obtain temperature measurements. The invention thus aims in particular at an integrator with a high reading dynamic, that is to say an integrator capable of measuring an electric current corresponding to a small quantity of electrical charges and of measuring an electric current corresponding to a large quantity of charges. electric. In particular, in the context of matrix detection, the invention aims at the formation of images containing the maximum of useful information, obtained from scenes presenting a high flow dynamics, that is to say characterized by large deviations of energy emitted between the various points of the scene, and more especially a particularly large difference in temperature between "cold" zones and "hot" zones with regard to thermal detectors, of the order of several hundred degrees Celsius . STATE OF THE ART The developments formulated below are based on the particular case of thermal detectors of the microbolometric type, in that they particularly benefit from the advantages provided by the invention. However, it should be noted that the problems expressed in this context apply to any type of device producing electrical charges to be measured. In particular, what is explained below applies to all electromagnetic radiation detectors, whether detectors operating for example in the visible range, or detectors operating in the infrared or beyond in the so-called Terahertz bands. Similarly, the invention also benefits from detectors sensitive to electromagnetic waves, such as thermal detectors for example of the bolometric and capacitive type, or coupling antennas for the thermal and Terahertz domains, and so-called quantum detectors, sensitive to corpuscles. electromagnetic energy among which we note the detectors operating from the X, UV, visible and infrared bands. In the context of the present invention, the term "detector" may be understood as any system intended to produce an electrical signal in relation to a unitary, linear or two-dimensional distribution of any phenomenon. In the field of so-called "thermal" infrared detectors, it is known to use one-dimensional or two-dimensional matrices of elements sensitive to infrared radiation, capable of operating at ambient temperature, that is to say not requiring cooling at room temperature. very low temperatures, unlike detection devices called "quantum detectors", which, they require operation at a very low temperature, typically that of liquid nitrogen.
    [0003] A thermal infrared detector traditionally uses the variation of a physical quantity of a suitable material called "thermometric" or "bolometric", depending on its temperature. Most commonly, this physical quantity is the electrical resistivity of said material which varies greatly with temperature. The unit sensitive elements of the detector, or "bolometers", usually take the form of membranes, each comprising a layer of thermometric material, and suspended above a substrate, generally made of silicon, via heat resistance support arms. high, the matrix of suspended membranes is usually referred to as the "retina". These membranes use, in particular, an absorption function of the incident infrared radiation, a function for converting the power of the radiation absorbed into heat output, and a thermometric function for converting the heating power produced into a variation of the resistivity of the thermometric material. these functions can be implemented by one or more distinct elements. In addition, the support arms of the membranes are also conductive and connected to the thermometric layer thereof. It is usually formed in the substrate above which the membranes are suspended, sequential means for addressing and polarizing the thermometric elements of the membranes, and means for forming the electrical signals that can be used in video formats. This substrate and the integrated means are commonly referred to as the "read circuit". In order to compensate for the drift in temperature of the detector, a solution generally implemented is the arrangement, in the electronic circuit for forming the signal in relation to the temperature of the imaging bolometers (so-called because sensitive to incident electromagnetic radiation), of a focal plane temperature compensation element (TPF) itself bolometric, that is to say whose electrical behavior follows the temperature of the substrate, but remains substantially insensitive to radiation. This result is obtained for example by means of bolometric structures endowed by construction of a low thermal resistance towards the substrate, and / or by masking these structures behind a screen that is opaque to thermal radiation. The implementation of these compensation elements also offers the advantage of eliminating most of the so-called common mode current from the imaging bolometers or "active". FIG. 1 is a circuit diagram of a bolometric detector 10 without temperature regulation, or "TECless" detector, of the state of the art, comprising a common mode compensation structure, and FIG. 2 is an electrical diagram of FIG. a circuit implemented to form a reading signal of a bolometer of the compensated common mode detector. Such a detector is for example described in the document: "Uncooled amorphous silicon technology enhancement for 25, a pixel pitch achievement"; E. Mottin et al, Infrared Technology and Application XXVIII, SPIE, vol. 4820E.
    [0004] The detector 10 comprises a two-dimensional matrix 12 of identical bolometric detection unit elements 14, or "pixels", each comprising a sensitive resistive bolometer 16 in the form of a membrane suspended above a substrate, as previously described. , and of electrical resistance Ra, each bolometer 16 is connected by one of its terminals to a constant voltage VDET, in particular the ground of the detector 10, and by the other of its terminals to a polarization MOS transistor 18 operating in steady state saturated, for example an NMOS transistor, adjusting the voltage Vac across the bolometer 16 by means of a gate control voltage GAC.
    [0005] If A designates the node corresponding to the source of the MOS 18 and if VA is the voltage at this node, which depends on the gate voltage GAC, the voltage Vac is then equal to Vae = VA-VDET. The pixel 14 also comprises a selection switch 20, connected between the MOS transistor 18 and a node S provided for each column of the matrix 12, and controlled by a control signal Select, allowing the selection of the bolometer 16 for its reading. The transistor 18 and the switch 20 are usually formed in the substrate under the influence of the membrane of the bolometer 16. The elements 16 and 18 form a so-called detection branch. In particular, since the pixels are identical and the voltage VDET on the one hand and the voltage GAC on the other hand are identical for all the pixels, the bolometers 16 are therefore biased in voltage under the same voltage Vac. In addition, the gate voltage GAC being constant, the voltage Vac is therefore also constant.
    [0006] The detector 10 also comprises, at the bottom of each column of the matrix 12, a compensation structure 22, also commonly referred to as a "skimming" or "skimming" structure. As described above, the value of the electrical resistance of the detection bolometers 16 is largely dictated by the temperature of the substrate. The current flowing through a detection bolometer 16 thus comprises a large component that depends on the temperature of the substrate and is independent of the observed scene. The compensation structure 22 has the function of producing an electric current for partial or total compensation of this component.
    [0007] The structure 22 comprises a compensation bolometer 24, electrical resistance Rem, made insensitive to incident radiation from the scene to be observed. The bolometer 24 is constructed using the same thermometric material as the bolometer 16, but has a very low thermal resistance towards the substrate. For example: the resistive elements of the compensation bolometer 24 are made directly in contact with the substrate, or the bolometer 24 comprises a membrane similar to that of the detection bolometers 16 suspended above the substrate by means of structures having a thermal resistance. very low, or else - the compensation bolometer 24 comprises a membrane and support arms substantially identical to those of the detection bolometers 16 and a good thermal conductive material fills the space between the membrane of the bolometer 24 and the substrate. The electrical resistance of the bolometer 24 is thus essentially dictated by the temperature of the substrate, the bolometer 24 is then said "thermalized" to the substrate.
    [0008] The bolometer 24 is connected at one of its terminals to a positive constant voltage VSK, and the compensation structure 22 further comprises a bias MOS transistor 26 operating in a saturated state, of opposite polarity to that of the transistors 18 of the detection 14, for example a PMOS transistor, adjusting the voltage Ven, across the bolometer 24 by means of a gate control voltage GCM, and connected between the other terminal of the compensation bolometer 24 and the node S. If denotes by B the node corresponding to the drain of the MOS 26 and by VB the voltage at this node, the voltage Ven, is then equal to Vem-VSK-VB. The elements 24 and 26 form a so-called compensation branch 35 common to each column. The value of the common compensation mode current is defined by the value of the resistor Rem of the bolometer 24 and the polarization parameters thereof.
    [0009] The detector 10 also comprises, at the bottom of each column of the matrix 12, an integrator 28 of the CTIA type (for the English expression "Capacitive Trans Impedance Amplifier") comprising for example an operational amplifier 30 and a single capacitor 32, of fixed Ga capacitance, connected between the inverting input and the output of the amplifier 30. The inverting input and the non-inverting input of the latter are furthermore connected respectively to the node S and to a positive constant voltage VBUS. The voltage VBUS thus constitutes a reference for the output signals, and is between VDET and VSK. A switch 34, driven by a Reset signal is also provided in parallel capacitor 32, for the discharge thereof. The outputs of the CTIA 28 are finally for example connected to respective sample and hold circuits 36 for the output of the voltages Vaut of the CTIA in multiplexed mode by means of a multiplexer 38 to an amplifier (s) output series 40. It can also be integrated at the output of digitization means by analog-to-digital converters (ADC).
    [0010] The detector 10 finally comprises a sequencing unit 42 controlling the various switches described above. In operation, the matrix 12 is read line by line. To read a line of the matrix 12, the switches 20 of the pixel line 14 are closed and the switches 20 of the other lines are open. The successive reading of all the rows of the matrix 12 constitutes a frame. For the reading of a bolometer 16 of a line of the matrix 12 selected for reading, after a phase of discharging the capacitors of the CTIA at the bottom of the column, made by closing the switches 34 by means of the Reset signal followed by their opening, it is thus obtained a circuit as shown in Figure 2 for each pixel of the line being read. A current / a, flows in the detection bolometer 16 of the pixel under the effect of its voltage polarization by the MOS transistor 18, and a current Ic 'flows in the compensation bolometer 24 of the compensation structure under the effect of its voltage bias by the MOS transistor 26. These currents are subtracted from each other at the node S, and the resulting currents difference is integrated by the CTIA 28 for a predetermined integration time Tint. The output voltage Vaut of the CTIA 28 thus represents a measurement of the variation of the resistance of the detection bolometer 16 caused by the incident radiation to be detected, since the non-useful part of the current / a, related to the temperature of the substrate, is compensated, at least in part, by the Icm current specifically produced to replicate this non-useful part.
    [0011] Assuming that the electrical resistances of the active bolometers 16 and compensation 24 are not significantly changed during their polarization by a self-heating phenomenon, and that the CTIA 28 does not saturate, the output voltage You of the integrator at the end of the integration time Tint is expressed by the relation: AT Vout = You Tc -1cm) dt = ac - cm) - T1n1 + VB US (1) C int C int As is known per se , a CTIA has a dynamic electrical output, or dynamic "reading", fixed. Below a first quantity of electrical charges received at the input, the CTIA delivers a fixed low voltage, called the "low saturation voltage" (VO). Similarly, above a second quantity of electric charges received at the input, the CTIA delivers a high fixed voltage called "high saturation voltage" (VsatH) .The relation (1) expresses the linear behavior of the CTIA, when it receives a quantity of electric charges higher than the first quantity of electrical charges, and lower at the second quantity of electric charges The reading dynamic is essentially fixed by the value of the capacitance Cuit of the capacitor 32. In particular, when this capacitance is fixed, that is to say constant in time, the dynamic of reading CTIA is also fixed By convention, in the context of the invention, the low saturation voltages Vsatt, and high VsatH are the limits between which the CTIA provides an output considered as linear, even though it is usually able to provide lower or higher voltages than these terminals. Moreover, the integration capability also determines the sensitivity, or more exactly the response (better known as "responsivity") of the detector. The response of a detector is defined by the variation of the output signal Vota in relation to the variation of the input signal (the scene temperature Tscene), ie dVout / dTscene. The observable dynamics of the scene, or "scene dynamics" is itself defined by the maximum temperature difference in a scene resulting in no saturation of the CTIA output signals, or, in other words, the difference between the most high temperature does not induce high saturation of CTIA and the lower temperature does not induce low saturation of CTIA. The sensitivity (response) of a detector is therefore the ability of the detector to detect the details of a scene while the detector's scene dynamics is its ability to transcribe without distortion very large temperature variations in a scene. . It is thus impossible to simultaneously optimize these two contradictory quantities with a fixed integration capacity.
    [0012] The state of the art proposes to favor one or the other of these magnitudes according to the intended application. Usually, the user opts for a high sensitivity, and the observable scene dynamics is necessarily reduced, for example to a few tens of degrees, either for a high stage dynamics, for example 200 ° C, and the detector has only a modest sensitivity regardless of the scene observed. In other words, the user sets the operating point of the detector so as to best meet his need for a compromise between sensitivity and scene dynamics.
    [0013] The foregoing considerations apply to any system forming an input signal electric current Ln, an example of which is the lac i cm difference described above, intended to be "read" by means of an integrator, in particular of the type CTIA. In this broad framework, it is a question of dealing with the inherent antagonism between the need for high acceptable dynamic input (here, at the level of the thermal scene) and the contradictory need for high gain of the signal formation chain which defines the sensitivity of the system, in particular the gain of the integrator dVout / dlin = TInt / Cint. Complex arrangements have been proposed to adapt the reading dynamics of an integrator to the quantity of electric charges that it receives. As part of an application in the field of detection, this allows to extend the dynamics of scene while maintaining a high sensitivity. Thus, the document Proc. of SPIE Vol. 6940, 694020, (2008) proposes to parallel two selectable capacitors in place of the single capacitor 32, a capacitor having a low capacitance and a capacitor having a high capacitance. For reading the unit detector array, a so-called "combined mode" is implemented. This mode alternates formation of a frame with a high gain by the selection of capacitors of low capacitance for CTIA, and therefore with high sensitivity, followed by the formation of a low gain frame by the selection of capacitors with high capacity for the CTIA, and therefore with great dynamic stage. The defect of this mode of operation resides in the limitation of the availability of broadband data in real time. Indeed, only one frame is displayed for three frames read. The frame rate is therefore one-third of the usual frame rate. of SPIE Vol. 6542, 65421R, (2007) discloses a matrix detector analogous to that previously described. However, it differs in a variable integration time depending on the position of the pixels. In particular, a high integration time is applied to a pixel, and a shorter integration time is applied to a pixel adjacent to this first pixel, the spatial distribution of the integration times being applied to the entire matrix in a pattern. in checkerboard. Once a frame read with the different integration times, a logic sequencer compares the signal from each pixel to a threshold. When the voltage from a pixel read with a high gain, that is to say with the high integration time, exceeds the threshold, this voltage is replaced in the frame by the average of the voltages from the neighboring pixels read with a low gain, that is to say with the low integration time. On the other hand, when the voltage from a pixel read with a low gain is below the threshold, this voltage is replaced in the frame by the average of the voltages from the neighboring pixels read with the high gain. It is easy to imagine the significant loss of information, especially concerning the details at high and low temperatures since the modified frame is an average.
    [0014] WO 2007/135175 discloses a pixel reset circuit of an image sensor, provided with CTIA for reading the electrical charges produced by the unitary detection elements. During the integration time, the output voltage of each CTIA is sampled successively three times at three fixed moments: the first sampled voltage serves to suppress the switching noise (called "kTC noise") of the two other voltages acquired, via a correlated dual sampling device (called "CDS" for "Correlated Double Sampling"); - the second voltage captures the details of the scene; and the third voltage makes it possible to manage a strong dynamic of the scene.
    [0015] The voltages thus obtained are then digitized and processed using a complex algorithm that applies a gain to the last two voltages once these corrected for the kTC noise and which chooses which will be proposed at the output so as to avoid the saturations and propose a maximum dynamic.
    [0016] This solution consumes a large amount of software and memory resources because of the extensive processing of the necessary information, external to the image sensor, and means of signal formation. In addition, this solution produces output information temporally offset with respect to the scene events, due to the multiple sampling and the time dedicated to the associated calculations. This defect is called "time inconsistency" or asynchronism.
    [0017] US 7,202,463 discloses a photodiode image sensor. For the reading of each photodiode, there is provided a capacitor connected in parallel thereof which integrates the electrical charges produced by the photodiode. A comparator is connected to the capacitor for comparing the voltage thereof to a threshold voltage and a capacitor discharge circuit connected to the output of the comparator discharges the capacitor when its voltage is greater than the threshold voltage. Finally, circuitry is also provided to count the number of threshold voltage overruns by the capacitor voltage during the integration period. The final signal is then restored by multiplying the threshold voltage by the number of counted exceedances, to which is added the final value of the voltage of the sensor capacitor. This system makes it possible to obtain a great dynamic of the scene, but because of the repeated discharge of the integration capacity, the final signal is tainted by a significant noise, the higher the number of discharges of the capacitor is high.
    [0018] DISCLOSURE OF THE INVENTION The object of the present invention is to propose a CTIA-based electrical current integrating device, which exhibits an extended reading dynamic without compromising the sensitivity of the system, while limiting the noise in the final signal. issued.
    [0019] For this purpose, the subject of the invention is a device for integrating an electric current received on an integration node for a predetermined period of time Tint, comprising an operational amplifier having a first and a second input and an output, and a capacitor having two terminals connected between the first input and the output of the operational amplifier, the second input of the amplifier being brought to a constant voltage VBUS, the first input of the amplifier being connected to the integration node, and the output of the operational amplifier delivering an output voltage V't which varies monotonically in a predetermined direction of variation as a function of a quantity of electrical charges of predetermined polarity stored in the capacitor, the voltage You output from the operational amplifier being saturated at a high saturation voltage VsatH when the quantity of electric charges of said polarity stored in the capacitor is greater than a predetermined threshold, and the voltage V't at the output of the operational amplifier being saturated at a low saturation voltage Vsaa, when the quantity of electric charges of said polarity stored in the capacitor It is less than a predetermined threshold. According to the invention, the device further comprises: a circuit for switching the terminals of the capacitor; and a triggering circuit of the switching circuit at least once during the integration time T1 when the output voltage You of the operational amplifier both varies according to said direction of variation and is substantially equal to a reference voltage VREF, o when said direction of variation is increasing, said reference voltage VREF being less than or equal to the high saturation voltage VsatH, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier are selected from to satisfy the relation 2. VBUS -VREF> Vsati,; or o when said direction of variation is decreasing, said reference voltage VREF being greater than or equal to the low saturation voltage VsatL, and the reference voltage VREF and the voltage VBUS of the second input terminal of the operational amplifier ( 62) are chosen so as to satisfy the relation 2. VBUS - VREF <VsatH - a storage circuit for storing the number of trips occurring between the initial instant and the final instant of the integration period. By capacitor terminal switching, or more simply, "switching of the capacitor", it is understood the momentary interruption of the electrical continuity between the armatures A1 and A2 of the integration capacitor and their respective connection nodes to the circuit N1 and N2 , then the formation of a new electrical continuity between Al and N2 and between A2 and Ni of the circuit.
    [0020] In other words, thanks to the switching of the capacitor, an automatic and autonomous extension of the reading dynamics of the CTIA is obtained as a function of the quantity of electric charges received, without modifying the sensitivity of the signal formation chain. , in particular the value of the capacitor and the integration time. When the output voltage of the CTIA reaches the reference voltage, the capacitor is switched off without being discharged. The conserved electrical charges define, as a result of the switching, a new voltage at the output of the CTIA, lower (when the output voltage is increasing) than that before switching, from which the integration continues. The useful output signal is determined as a function of the number of switches, the decrement (or increment) of voltage produced by switching and optionally the output voltage of the CTIA at the end of the integration time.
    [0021] In addition, since the capacitor is never discharged, the noise is limited. In addition, the device forms an image signal in time coherence with the received charges, without recourse to complex digital and / or algorithmic processing subsequent to the formation of signals from several pixels. In addition, the additional circuits implemented compared to a simple CTIA are very low energy consumption and substrate surface, and dynamic extensible as needed. Advantageously, the number of switches performed over the integration time span and the output voltage of the CTIA are delivered jointly for each detection site.
    [0022] In particular, according to an advantageous characteristic of the invention, the storage circuit produces at output an n-bit digital signal encoding the number of electrical charges to be added to the load corresponding to the analog signal at the output of the CTIA at the end of the period. integration.
    [0023] According to one embodiment, the switching circuit comprises: a first controllable switch connected between the first input of the operational amplifier and the first terminal of the capacitor; a second controllable switch connected between the output of the operational amplifier and the second terminal of the capacitor; a third controllable switch connected between the first input of the operational amplifier and the second terminal of the capacitor; a fourth controllable switch connected between the output of the operational amplifier and the first terminal of the capacitor, and the first and the second controllable switches are controlled by a first binary control signal, the third and fourth controllable switches are controlled by a second binary control signal, the second binary signal being the complement of the first binary signal. According to one embodiment, the trigger circuit comprises a comparator having a first input connected to the output of the amplifier and a second input connected to the reference voltage, the comparator producing a first voltage on its output when the voltage on its first input is lower than the voltage on its second input, and producing a second voltage, different from the first voltage, on its output when the voltage on its first input is greater than the voltage on its second input, so that a condition necessary to trigger the switching circuit implemented by the tripping circuit is performed: - when switching from the first voltage to the second voltage if said direction of variation is increasing; or - when switching from the second voltage to the first voltage if said direction of variation is decreasing. According to one embodiment, the triggering of the switching of the capacitor implemented by the tripping circuit consists in the meeting of: a first sub-condition that the output voltage of the operational amplifier varies according to said sense of variation and is substantially equal to the reference voltage; and a second sub-condition that the number of times the first sub-condition has been satisfied since the initial time of the integration time is less than a predetermined maximum number. More particularly, the tripping circuit comprises an n-bit bit counter having a counting input connected to the output of the comparator and an output delivering the number of times since the initial time of the integration duration Tint where the comparator output flipping from the first voltage to the second voltage when said direction of variation is increasing or toggles from the second voltage to the first voltage when said direction of variation is decreasing.
    [0024] The maximum number of switches of the second sub-condition, strictly greater than 1, is determined according to the intended application. In particular, it may be sufficiently large so that the maximum number of switches is rarely or never reached in practice and the number of switches is therefore in practice determined by the end of the integration period.
    [0025] In particular, the tripping circuit comprises a signal generator connected to the output of the binary counter and switching the first and second binary control signals of the switches when the output of the binary counter is incremented.
    [0026] The invention also relates to an electromagnetic radiation detection system comprising: a detection element producing on an output terminal an electric current as a function of the electromagnetic radiation; and a device of the type described above, the first input terminal of the operational amplifier being able to be connected to the output terminal of the detection element for the integration of the current produced by the element of detection.
    [0027] In particular, the detection element comprises: a detection branch, comprising a detection bolometer having a membrane suspended above a substrate and a bias circuit for adjusting the voltage across the detection bolometer as a function of a voltage setpoint; a compensating branch, comprising a compensation bolometer carried substantially at the temperature of the substrate, and a bias circuit for adjusting the voltage across the compensation bolometer as a function of a voltage setpoint; and means for forming the difference between the current flowing through the detection bolometer and the current flowing through the compensation bolometer so as to form the electric current to be integrated. The invention also relates to a method of integrating an electric current during a predetermined integration time Tua into a capacitor having two terminals connected between a first input and the output of an operational amplifier, the operational amplifier comprising a second input brought to a constant voltage VBUS, the voltage You output from the operational amplifier monotonically varying in a predetermined direction of variation as a function of a quantity of electrical charges of predetermined polarity stored in the capacitor, said voltage in When you are saturated at a high saturation voltage VsatH when the quantity of electrical charges stored in the capacitor is greater than a predetermined threshold, and the output voltage Vs of the operational amplifier is saturated at a low saturation voltage VsatL when the quantity of electric charges of said pola The method comprises the following steps: a) before the initial time of the integration time Tait, zero initialization of the capacitor charge and a count value; b) integration during the integration time Tua of the electric current in the capacitor; c) switching the capacitor terminals at least once during the integration time Tua when both the output voltage of the operational amplifier varies in the said direction of variation and is equal to a predetermined reference voltage VREF, o when said direction of variation is increasing, said reference voltage VREF being less than or equal to the high saturation voltage VsatH, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier (62) are selected from to satisfy the relation 2. VBUS - VREF> VsatL; or o when said direction of variation is decreasing, said reference voltage VREF being greater than or equal to the low saturation voltage VsatL, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier are chosen so to satisfy the relation 2. VBUS - VREF <VsatH; d) incrementing a unit of the count value following each switching of the capacitor during the integration time Tmt; e) after the final instant of the integration time T ,, t, delivery of the count value.
    [0028] According to one embodiment, the condenser is switched as long as the count value is less than a predetermined maximum value. BRIEF DESCRIPTION OF THE FIGURES The invention will be better understood on reading the description which will follow, given solely by way of example, and made with reference to the appended drawings, in which like references designate identical or similar elements, and in which: FIG. 1 is a circuit diagram of a prior art infrared bolometric detector comprising CTIA type integrators for measuring the currents produced by the detection elements, already described above; FIG. 2 is an electrical diagram illustrating the reading of a sensitive bolometer of the detector of FIG. 1 with the aid of a compensation structure; FIG. 3 is an electrical diagram of an electric current integration device according to the invention; FIG. 4 is a timing diagram illustrating the output signal of the integration stage and the reset signals of the device of FIG. 2; and FIG. 5 is a timing diagram illustrating an extension of the reading dynamics of the device of FIG. 3 in the context of using this device as a device for integrating a matrix detector.
    [0029] DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 3, an integration device 60 according to the invention comprises a CTIA type integrator comprising an operational amplifier 62 and a single capacitor 64, of fixed capacitance Cmt, connected between the inverting input and the output of the amplifier 62. The non-inverting input (+) thereof is connected to a positive and constant voltage VBUS and the inverting input (-) is connected to the input node or integration E through which circulates an electric current I to integrate.
    [0030] A switch 66, driven by a signal HDraz, is also provided in parallel with the capacitor 64, for the discharge thereof, and therefore its "reset".
    [0031] The device 60 is supplemented with a sample-and-hold device 68 connected to the output of the operational amplifier 62 for sampling and blocking the voltage Go at the output of the latter.
    [0032] In addition to the integrating stage CTIA described above, the device 60 is completed by a circuit 70 for automatically extending the reading dynamics of the single CTIA 62, 64. This circuitry 70 comprises: a circuit 72 reversing the direction of the connecting the capacitor 64 to the terminals of the operational amplifier 62 on receipt of a control signal HD [2: 0]; a circuit 74 detecting a switching condition of the capacitor 64 as a function of the voltage V't at the output of the amplifier 62 and generating the control signal HD [2: 0]; and a circuit 76 memorizing the number of switching operations of the capacitor 64.
    [0033] The switching circuit 72 comprises: a first controllable switch 78 connected between the inverting input (-) of the amplifier 62 and a first terminal 80 of the capacitor 64, the first switch being controlled by a first control signal HDinv; a second controllable switch 82 connected between the output 84 of the amplifier 62 and a second terminal 86 of the capacitor 64, the second switch being controlled by the first control signal HDinv; a third controllable switch 88 connected between the inverting input (-) of the amplifier 62 and the second terminal 86 of the capacitor 64, the third switch being controlled by a second control signal HDinv; a fourth controllable switch 90 connected between the output 86 of the amplifier 62 and the first terminal 80 of the capacitor 64, the fourth switch being controlled by the second control signal HDinv; and a phase generator 92 receiving the HD [2: 0] control signal and producing the HDinv and HDinv control signals in accordance therewith.
    [0034] In particular, the HDinv and HDinv signals are in phase opposition. For example, they are binary signals that are logical complements to each other. Thus, the first and second switches 78, 82, which have the same state, are open while the third and fourth switches 88, 90, which have the same state, are closed and vice versa. Two connection states of the capacitor 64 are thus defined, namely: a first state in which the first and second terminals 80, 86 of the capacitor 64 are respectively connected to the node E and to the output 84 of the amplifier 62, and a second state in which the first and second terminals 80, 86 of the capacitor 64 are respectively connected to the output 84 of the amplifier 62 and to the node E. The switching of the signal HDinv, and therefore of the signal HDinv, therefore causes the inversion of the connection state of the capacitor 64, that is to say its switching. The phase generator 92 also produces the HDraz signal driving the reset switch 66 of the capacitor 64 as a function of a reset initialization signal RAZ in a manner explained hereinafter.
    [0035] The phase generator 92 also implements a function for activating and deactivating the automatic reading dynamics extension mode according to an HD MODE ON mode selection signal, in a manner which will also be described. below.
    [0036] The detection circuit 74 comprises: a comparator 94 receiving at a first terminal (+) the voltage Vout at the output of the amplifier 62 and at a second terminal (-) a reference voltage VREF greater than the voltage VBUS and less than or equal to the high saturation voltage VsatH of the CTIA.
    [0037] The comparator 94 outputs a voltage Scomp having a first value when the voltage Vout is lower than the voltage VREF, and having a second value, different from the first value, when the voltage Vout is greater than or equal to the voltage VREF. In particular, the switching of the voltage Scomp from the first value to the second value means that the voltage Vout is increasing and has just crossed the reference voltage VREF; a bit counter 96, whose counting input is connected to the output of the comparator 94. The binary counter is for example designed to count the rising edges of the pulses, the second voltage value of the comparator then being chosen greater than the first voltage value. The counter 96 has a predetermined number of bits, for example 4, and receives on an initialization terminal the reset signal RAZ for resetting it. Moreover, the counter 96 is configured to be blocked once its maximum value has been reached. Finally, the signal at the output of the bit counter 96, which is for example delivered on 3 outputs in parallel, an output being provided for each bit of the counter, provides the control signal HD [2: 0] of the phase generator 92.
    [0038] The storage circuit 76 is constituted for example by an asynchronous digital memory of the "LATCH" type, which receives the value of the counter contained in the signal HD [2: 0] and maintains this value in its output signal HDsh [2: 0]. The storage circuit 76 and the sample-and-hold device 68 are driven by the same sampling signal FSH for maintaining the output signals received at the output. Finally, the integration device 60 according to the invention advantageously comprises an "autozero" circuit 98 connected to the inverting input (-) of the amplifier 62, in order to cancel the offset of the amplifier 62 and the low frequency noise thereof in a manner known per se, and for example described in the document IEEE Journal of Solid-state circuits, vol. sc-20, No. 3, June 1985. The operation of the device 60 goes to present be described in relation with FIGS.
    [0039] Before starting a phase of integration of an electric current I (phase "A"), the signals HDraz and HDinv are activated high by the generator 92 upon receipt of a predetermined value of the command RAZ, the complemented signal HDinv thus also being brought to the low state by the generator 92. The switches 66, 78 and 82 are therefore in their closed state, the switches 88, 90 are in their open state and the outputs HD [2: 0] counter 96 are set low. Closing switch 66 discharges capacitor 64, and following this reset, the output voltage You is equal to VBUS. Since the voltage VREF is greater than the voltage VBUS, the output of the comparator 94 is thus set to its lowest value. During this initialization phase, during which the HDraz signal is activated in the high state, the autozero system 98 is also implemented in a manner known to those skilled in the art. The reset command is then released, the generator 92 triggers the opening of the switch 66 and retains the state of the signals HDinv and HDinv. The opening of the switch 66 thus marks the beginning of the phase of integration of the current I received at the input (phase "B"), the autozero system 98 is active to subtract the offset at the input of the amplifier 62 throughout the integration phase. The generator 92, and the switch 66 thus form an initialization circuit of the device which determines the instant of the beginning of the integration period from the falling edge of the RAZ signal to the rising edge of the RAZ signal which marks the final moment of the integration period. Due to the integration, the voltage V output of the amplifier 62 increases since the value VBUS (phase "B 1").
    [0040] If, during the entire duration integration phase Tait, the voltage remains below the reference voltage VREF, no new logic condition appears at the output of the binary counter 96. The operation of the device 60 is then identical to that of a CTIA of the state of the art, as described in relation to Figures 1 and 2, and the output signal HD [2: 0] remains low. On the other hand, if during the integration phase, the output voltage V't reaches or exceeds the value VREF, the output Scomp of the comparator 94 changes state, which propagates the high state at the output of the comparator. input of the clock of the binary counter 96, which then activates the low-order bit HD0 to 1. We then have HD [2: 0] = 001. The switching of a bit of the signal HD [2: 0] of the low state in the high state is detected by the phase generator 92. In response, the latter switches the control signals HDinv and HDinv respectively on the low state and the high state. This results in the switching of the capacitor 64 connections between the amplifier 62 and the autozero circuit 98. At the moment when the condition V't = VREF is fulfilled, the quantity of electric charges Q stored in the capacitor 64 is equal to: Q Cint. (VREF-VBUS) (2) After the switching of the capacitor 64, the load Q across the CTIA is of inverse polarity to that presented before switching, so that the output of the amplifier 62 is equal to : V't = 2.VBUS-VREF (3) The output of the comparator 94 then switches to the low state since the voltage V't is strictly lower than the reference voltage VREF. Switching capacitor 64 thus returns the output of amplifier 62 to a lower level. In order not to saturate the CTIA, the voltage VBUS and the voltage VREF are chosen so as to satisfy the relation: 2. VBUS - VREF> V satL For example, the voltage VBUS is set above, and advantageously at the central point of A linear dynamic of the CTIA, the VBUS voltage thus satisfying the relationship: VBUS> Vsati, VsatH 25 2 Beyond this moment, the integration phase continues (phase "B2"), the output of the amplifier 62 resuming its growth in the linear dynamics of reading, without any loss of information.
    [0041] If the output Vont of the amplifier 62 reaches or exceeds the value VREF before the end of the integration, the Scomp output of the comparator 94 changes polarity again and increments the counter 96 again. The binary output of the latter is then set to HD [2: 0] = 010.
    [0042] On receipt of the switching of a bit of the signal HD [2: 0], the generator 92 switches the signals HDinv and HDinv, in this case respectively in the high state and the low state, which causes the switching of the capacitor 64. The electric charge Q at the terminals of the CTIA is again of reverse polarity with respect to that presented before the switching, and the output of the amplifier 62 is thus reduced to V't = 2.VBUS-VREF and the output of the comparator 94 switches to the low state since V't <VREF. A new phase of growth of the output You since the value 2. VBUS-VREF is then implemented (phase "B3"). The capacitor can thus switch repeatedly without loss of information up to the maximum value of the binary counter 96, for example here on 3 bits, ie the maximum value HDSH [2: 0] = 111.
    [0043] Once the integration time Tint has elapsed, the output voltage You (T ') is sampled and blocked in the sample-and-hold circuit 68 by sending a pulse for the signal FSH, as in the integration mode. conventional, while the binary values of the signal HD [2: 0] are also stored in a latch-type memory stage 76 on receipt of the pulse of the same signal FSH. The device 60 thus delivers, at the end of an integration phase, a signal HDSH [2: 0] representing the number of commutations of the capacitor 64 as well as the voltage VoittsH equal to the output voltage of the amplifier 62. The signal FSH is for example activated in the high state by a digital control signal management circuit (not shown) for a short period just before the end of the integration, that is to say before the rising edge of the signal Reset, as shown in Figures 4B and 4C, which also specify the start and end times of the integration period. Other mechanisms for setting the start and end times of the integration time are of course possible. The capacity Cmt of the CTIA stage and the binary counter can then be reset to zero by activating the reset command before a new integration cycle, as previously indicated.
    [0044] Finally, the total voltage Vjultnalcorresponding to the electrical charges integrated by the CTIA 62, 64 during the integration phase is therefore equal to: vofuttnal = v outSH + 2. convio (HpsH [2: 0]) x (VREF - VBUS) (4) where convio (HDsH [2: 0]) is the conversion to the decimal value of HDSH [2: 0], that is, the number of capacitor switches. The equivalent reading dynamics can therefore be automatically increased by the value 2e). (VREF-VBUS), or in other words multiplied by 2n, where n is the number of bits of the binary counter 96, which can correspond to a dynamic much higher than that of a conventional CTIA, depending on the maximum value of the binary counter used and the value of the reference voltage VREF.
    [0045] Several variants are possible for the operation of the signals HDSH [2: 0] and VoutSH. In a first variant, a conversion system and a calculation unit complete the device 60. The conversion unit converts the HDSH [2: 0] and VoutsH signals into digital values, and the calculation unit calculates a digital final voltage. according to the digital values of the signals HDsH [2: 0] and VoutsH based on the relation (4). In a second variant, a digital-to-analog converter and an adder complete the device 60. The converter produces an analog voltage equal to 2. convio (HDsH [2: 0]) x (VREF - VBUS) as a function of the signal HDsH [2 0], and the adder adds the voltage thus produced with the voltage VoutsH, or directly the voltage Vout at the output of the amplifier 62. In a third variant, a single video output is used for the implementation of the detector according to the invention.
    [0046] In a fourth variant, only the signal HDsH [2: 0] is delivered, which is then considered as a digital conversion of the analog current received as input. The device according to the invention is therefore in this context an analog-digital converter. The number of bits of the counter and the value VREF are then chosen to define the quantization step of the converter, as well as its dynamics.
    [0047] The initial design, then the configuration or variable programming in use of a detector according to the invention is easily achievable by those skilled in the art, by means of the usual architectures and protocols for digital programming of modern detectors, for example validation or the very simple and immediate on-demand inhibition of the "extended dynamic" function, or the forcing from outside one of the possible values of the total equivalent integration capacity (2 ".Gt). binary information according to one or more digital bits indicating synchronously to the output signal if a given pixel has been "saturation" or not is available in parallel with the analog video output. convenient and fast all image data, such as video representation (immediate serial data management for controlled operation in the dy Namique display for example) or any other use information or analog or digital processing of the data stream, in connection with the occurrence of a phenomenon of "saturation" local. For example, in the context of a bolometric detector, as described in connection with Figures 1 and 2, the CTIA 28 are replaced by devices 60 just described. For example, the sample-and-hold devices 68 of the devices 60 are the sample-and-hold devices 36 and a second multiplexer is provided to output the 1-1DsH [2: 0] signals in multiplexed mode. A conversion unit and a calculation unit then complete the detector to digitally reconstruct the final voltage from each pixel 14. FIG. 5 represents an example of output of the binary signals HD [2: 0] in a particular case where three pixels "Pix i + 4", "Pix i + 7" and "Pix i + 8", in any multiplexed sequence, would have triggered the extension of the dynamics according to the invention by causing one to several times the switching of the capacitor 46. In the context of an application to detection, the invention thus makes it possible to maintain optimum sensitivity on the zones made up of all the pixels that do not cause the VREF reference voltage to be crossed, that is, that are not saturating, VREF being chosen less than or equal to the saturation voltage VsatH, while providing a usable signal on the areas of the image where the scene temperature is such that it would have saturated the voltage inoutput of the amplifier 62 in the absence of the invention, that is to say, too high compared to the dynamics of scene (thermal here) nominal. The exit would have been on these areas deprived of information relating to the scene observed. It is thus obtained at the same time a high sensitivity and a high dynamics of scene.
    [0048] According to an advantageous characteristic of the invention, the extension of the reading dynamics implemented by the integration device according to the invention can be activated or deactivated from the outside, for example by means of manual control or in a software way, by a digital input "HD MODE ON", as illustrated in FIG. 3, transmitted by means of a programming interface, for example the interface of which the detector reading circuits are usually provided. state of the art, or programmed directly externally by a dedicated input. The reading circuit incorporating the device according to the invention can thus be used at any time either in normal mode, that is to say in accordance with the operating mode described with reference to FIGS. 1 and 2, or in " extended scene dynamics ". Typically, this command "HD MODE ON" forces the low level at the output of the comparator 94, and therefore, the counter 96 never changes state, and the switching of the capacitor 64 is never activated. It will be noted that the adjustment of the voltage VREF to any value greater than the maximum output voltage of the CTIA (generally greater than VsatH by the above-mentioned linearity conventions) also produces the effect of inhibiting the extension. of the scene dynamics of the sensor because the Scomp output of the comparator 94 is kept low. Forcing VREF to the same value as the supply voltage of the amplifier will also have this inhibiting effect on the dynamic extension device. It has been described a single capacitor 64. In a variant, a plurality of capacitors are provided in parallel and selectable in a programmed manner so as to form a programmable integrated integration capacitor with several values in a manner known per se of the state of the art. This makes it possible to respond to different areas of application of the detector and offers the user an external adjustment of the scene dynamics. In this embodiment, the variation of the capacitance Cmt is also plotted in order to reconstitute the final voltage, the reconstruction being within the reach of those skilled in the art.
    [0049] A 3-bit binary counter has been described. Obviously, the number of bits of the counter depends on the intended application. In addition, the number of bits can be chosen very large so as never to reach the maximum value thereof. Similarly, other types of counting circuit can be envisaged. For example, the output of the comparator 62 is directly connected to the input of the generator 92 which drives the different signals as a function of the switching of the output of the comparator, and the output of the comparator is delivered to an information processing unit which stores the number of commutations. The maximum number of switches is thus dictated by the storage capacity of this unit and can be almost infinite.
    [0050] It has been described a particular application that the polarity of the integrated current and the architecture of the integration device causes an increase in the voltage Go output of the operational amplifier as a function of the amount of charge stored in the capacitor. Alternatively, the polarity of the current and / or the architecture of the integration device induces a decrease in the voltage at the output of the amplifier as the amount of charge stored in the capacitor increases. In such an embodiment, the voltage VREF is chosen greater than or equal to the low saturation voltage Vsad, and the voltage VBUS is chosen so as to satisfy the relation 2. VBUS - VREF <VsatH. The comparator at the output of the amplification then switches from a first value to a second value when the voltage T is decreasing and equal to VREF, this switching being counted by the binary counter and causing the switching of the capacitor. It has been described a reference voltage VREF constant over time. In a variant, this voltage is also programmable, its value being able to vary during the integration phase itself. According to a very simplified implementation variant, by adjusting the values of the capacitance Cmt and of the reference voltage VREF (depending on the product) in an integrated manner in the architecture / internal wiring of the read circuit, the user There is nothing to predict in terms of acquisition protocol and / or information processing to simultaneously have an extended dynamic and a high sensitivity, hence an extreme ease of use. A detector using the invention to integrate the electric current from a sensitive site, for example a bolometer, has a certain number of advantages over the prior art readout circuits, in particular: access to extended scene dynamics while maintaining a high sensitivity on the part of the image that is transcribable in the nominal electrical dynamics of the CTIA alone while the linearity of the signal as a function of the flux is retained unlike some logarithmic response systems for example ; - The frame rate (defined by the number of times the whole matrix is read in one second) is kept identical to the usual standards (60Hz for example). In other words, there is no degradation of the information temporal density with respect to some state-of-the-art forms of dynamic extension: the scene information obtained is maintained in temporal coherence, or synchronicity, permanent with the scene. Indeed, the space of time separating any event on the scene and the formation of the signal usable by the observer or the system using the output flow of the Vout signals, does not exceed a frame time, unlike all the detectors or systems whose data stream is over-sampled and / or computationally processed after forming the raw signals to obtain the information deemed exploitable with extended dynamic; - a simplification of the use of the detector. Indeed, in the state of the art, the user must generally himself choose the operating point of the detector according to the range of observed scene temperatures. In general, to give an idea, three different operating points are necessary to cover the dynamics [-40 ° C; +1000 ° C] without saturation; compared to the methods of the technical field based on the adaptation of the integration time, the invention provides the advantage of not modifying the thermal cycle of the bolometer imposed by the Joule self-heating during the cycle of integration. This characteristic is particularly appreciable as to the stability of the continuous level as a function of ambient thermal operating conditions, in particular when small differences in the temperature of the scene are sought with good temporal stability. The effectiveness of the possible implementation of the detector without Peltier stabilization module (so-called TEC-less operation in English), more and more common in the field, is therefore retained; - There is no reset noise at zero when inverting the integration capacity, as in some forms of the prior art, because the latter is never emptied, until after the moment where the signal is sampled; Moreover, the parasitic capacitances which represent, for example, the gates of the connection switches and the connections themselves form an integral part of the integration capacitance and do not add in themselves any parasitic disturbance. The signal formed at the output therefore does not lose any form of quality as a result of the application of the invention.
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. A device (60) for integrating an electric current received on an integration node for a predetermined period of time Tint, comprising an operational amplifier (62) having a first and a second input and an output, and a capacitor (64) ) having two terminals connected between the first input and the output of the operational amplifier (62), the second input of the amplifier being brought to a constant voltage VBUS, the first input of the amplifier being connected to the integration node , and the output terminal of the operational amplifier delivering an output voltage V't which varies monotonically in a predetermined direction of variation as a function of a quantity of electrical charges of predetermined polarity stored in the capacitor (64), the voltage You output from the operational amplifier (62) being saturated at a high saturation voltage VsatH when the quantity of electrical charges d e said polarity stored in the capacitor (64) is greater than a predetermined threshold, and the voltage V't at the output of the operational amplifier (62) being saturated at a low saturation voltage VsatL when the quantity of electrical charges of said polarity stored in the capacitor (64) is less than a predetermined threshold, characterized in that the device (60) further comprises: - a circuit (72) for switching the terminals of the capacitor; and a circuit (74) for triggering the switching circuit (72) at least once during the integration time Tua when the output voltage V't of the operational amplifier (62) both varies in said direction variation and is substantially equal to a reference voltage VREF; and - a memory circuit (76) for storing the number of trips occurring between the initial time and the final time of the integration period. and in that: - when said direction of variation is increasing, said reference voltage VREF is less than or equal to the high saturation voltage VsatH, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier (62) are chosen to satisfy the relationship
    [0002]
    2. VBUS -VREF> VsatL; OR - when said direction of variation is decreasing, said reference voltage VREF is greater than or equal to the low saturation voltage VsatL, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier (62) are chosen to satisfy the relation 2. VBUS VREF VsatH - 2. Device for integrating an electric current according to claim 1, characterized in that: the switching circuit (72) comprises: a first controllable switch ( 78) connected between the first input of the operational amplifier (62) and the first terminal of the capacitor (64); a second controllable switch (82) connected between the output of the operational amplifier (62) and the second terminal of the capacitor (64); a third controllable switch (88) connected between the first input of the operational amplifier (62) and the second terminal of the capacitor (64); a fourth controllable switch (90) connected between the output of the operational amplifier (62) and the first terminal of the capacitor (62), and in that: the first and the second controllable switches (78, 82) are controlled by a first binary control signal HDinv; the third and fourth controllable switches (88, 90) are controlled by a second binary control signal HDinv, the second binary signal HDinv being the complement of the first binary signal HDinv.
    [0003]
    Electrical current integrating device according to claim 1 or 2, characterized in that the tripping circuit (74) comprises a comparator (94) having a first input connected to the output of the operational amplifier (62). ) and a second input connected to the reference voltage VREF, the comparator (94) producing a first voltage on an output when the voltage on its first input is lower than the voltage on its second input, and producing a second voltage, different from the first voltage, on the output when the voltage on its first input is greater than the voltage on its second input, so that a condition necessary for triggering the switching circuit (72) implemented by the circuit (74) of triggering is performed: - when switching from the first voltage to the second voltage if said direction of variation is increasing; or - when switching from the second voltage to the first voltage if said direction of variation is decreasing.
    [0004]
    4. Device for integrating an electric current according to one of the preceding claims, characterized in that the triggering of the switching of the capacitor (64) implemented by the trip circuit (74) consists of meeting: - d a first sub-condition that the output voltage You of the operational amplifier (62) varies in said direction of variation and is substantially equal to the reference voltage VREF; and a second sub-condition that the number of times the first sub-condition has been satisfied since the initial time of the integration period T7 is less than a predetermined maximum number.
    [0005]
    Electrical current integrating device according to claim 4, characterized in that the tripping circuit (74) comprises an n-bit bit counter (96) having a counting input connected to the output of the comparator (94). ) and an output delivering the number of times since the initial time of the integration time Tint where the output of the comparator (94) switches from the first voltage to the second voltage when said direction of variation is increasing or toggles the second voltage at the first voltage when said direction of variation is decreasing.
    [0006]
    6. Device for integrating an electric current according to claims 2 and 5, characterized in that the tripping circuit (74) comprises a signal generator (92) connected to the output of the binary counter (94) and tilting the first and second binary control signals HDinv, HDinv switches (78, 82, 88, 90) when the output of the binary counter (94) is incremented.
    [0007]
    An electromagnetic radiation detection system comprising: - a detection element (14, 22) producing on an output terminal (S) an electric current as a function of the electromagnetic radiation; and a device (60) according to any one of the preceding claims, the first input of the operational amplifier (62) being connected to the output terminal (S) of the detection element (14, 22) for integration of the current produced by the sensing element.
    [0008]
    An electromagnetic radiation detection system according to claim 7, characterized in that the detection element comprises: - a detection branch (14), comprising a detection bolometer (16) having a membrane suspended above a substrate and a bias circuit (18) for adjusting the voltage across the detection bolometer (16) as a function of a voltage setpoint; a compensation branch (22), comprising a compensation bolometer (24) substantially raised to the temperature of the substrate, and a bias circuit (26) for adjusting the voltage across the compensation bolometer (24) as a function of a voltage setpoint; andmeans for forming the difference between the current i 'traversing the detection bolometer (16) and the current G, traversing the compensation bolometer (24) so as to form the electric current to be integrated.
    [0009]
    A method of integrating an electric current for a predetermined integration time T7 into a capacitor (64) having two terminals connected between a first input and the output of an operational amplifier (62), the operational amplifier comprising a second input brought to a constant voltage VBUS, the output voltage of the operational amplifier (62) monotonically varying according to a predetermined direction of variation as a function of a quantity of electrical charges of predetermined polarity stored in the capacitor ( 64), said output voltage being saturated at a high saturation voltage VsatH when the amount of electrical charges stored in the capacitor (64) is greater than a predetermined threshold, and the output voltage of the operational amplifier (62 ) being saturated at a low saturation voltage VsatL when the quantity of electric charges of said polarity stored in the capacitor (64) is less than a predetermined threshold, the method comprising the following steps: a) before the initial time of the integration time T ,, t, zero initialization of the capacitor charge (64) and a count value; b) integration during the integration time T1 of the electric current in the capacitor (64); c) switching of the capacitor terminals at least once during the integration time T7 when both the output voltage of the operational amplifier (62) varies in the said direction of variation and is equal to a predetermined reference voltage VREF, o when said direction of variation is increasing, said reference voltage VREF being less than or equal to the high saturation voltage VsatH, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier (62) are chosen to satisfy the relation 2. VBUS - VREF> VsatL; or o when said direction of variation is decreasing, said reference voltage VREF being greater than or equal to the low saturation voltage VsatL, and the reference voltage VREF and the voltage VBUS of the second input of the operational amplifier (62) are chosen to satisfy the relation 2. VBUS - VREF <VsatH; d) incrementing a unit of the count value following each switching of the capacitor (64) during the integration time Tua; ande) after the final time of the integration time T ,, t, delivery of the count value.
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    同族专利:
    公开号 | 公开日
    FR3020906B1|2018-11-02|
    JP2017515354A|2017-06-08|
    EP3140906B1|2020-12-02|
    CN106134072A|2016-11-16|
    CN106134072B|2019-02-22|
    WO2015170041A1|2015-11-12|
    US10199990B2|2019-02-05|
    US20170111015A1|2017-04-20|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1454119|2014-05-07|
    FR1454119A|FR3020906B1|2014-05-07|2014-05-07|HIGH DYNAMIC DEVICE FOR THE INTEGRATION OF AN ELECTRICAL CURRENT|FR1454119A| FR3020906B1|2014-05-07|2014-05-07|HIGH DYNAMIC DEVICE FOR THE INTEGRATION OF AN ELECTRICAL CURRENT|
    EP15759830.1A| EP3140906B1|2014-05-07|2015-04-30|High dynamic range device for integrating an electrical current|
    JP2016559557A| JP2017515354A|2014-05-07|2015-04-30|High dynamic range device for integrating current|
    CN201580017768.2A| CN106134072B|2014-05-07|2015-04-30|High dynamic range device for being integrated to electric current|
    PCT/FR2015/051164| WO2015170041A1|2014-05-07|2015-04-30|High dynamic range device for integrating an electrical current|
    US15/300,641| US10199990B2|2014-05-07|2015-04-30|High dynamic range device for integrating an electrical current|
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